"We've moved beyond the era of two dimensional chips.  The costs in terms of power consumption, performance, functionality and die size are simply to great to continue development on that path.  The next wave of chip innovation will center around 3D die stacking, with through silicon vias and very fine grained alignment.  This is absolutely nothing short of a revolution in semiconductor development.

Chips will never be the same!"

"We have reached the perilous edge of die area expansion.  Since we can't keep pushing out, we have to move up.  The Z dimension allows us to increase performance and functionality, while keeping power, costs and package size low.  4D Chips has assembled an ecosystem of expert partners, backed by patented manufacturing innovation, that will enable virtually unlimited vertical integration.

The next wave is UP!"

Community Resources

Articles & Presentations:

  •  3D stacked chip technology using bottom-up electroplated TSVs — In this paper from ECTC 2009, the authors report on using bottom-up electroplating for TSV fabrication.  They also present a process flow for 3D chip stacking.

  •  A Study of Through-Silicon-Via impact on the 3D stacked IC layout — This paper appears in Computer-Aided Design - Digest of Technical Papers, 2009. ICCAD 2009.   The authors "propose a new force-directed 3D gate-level placement that efficiently handles TSVs. In addition, they "present an algorithm that assigns TSVs to nets to complete routing that involves TSVs."

  •  Driving Down the Cost of TSVs — Semiconductor International has a great article covering the progress towards driving down the cost of the entire TSV process flow.

  •  EMC3D Library — The Semiconductor 3-D Equipment and Materials Consortium (EMC3D) has a wonderful library of material, including 3D Cost of Ownership, Market Analysis 3D, Technical Presentations and Industry Publications.

  •  Perspectives From the Leading Edge (Blog) — "Dr. Phil Garrou gives his perspective and insight into developments in 3-D integration and advanced packaging, reporting the latest technical goings on from conferences, conversations, and more."

  •  Through Silicon Vias (TSV):  Design and Reliability (PDF) — A very interesting slide deck from our friends at ALLVIA, the TSV foundry specialists.  The pictures alone more than justify a look!

  •  TSV makes EETimes 2010 Hot Tech List — EETimes reports that, "The desire, for marketing as well as technical reasons, to mount multiple die in single packages is also driving a need for more sophisticated interconnect and the arrival of the through-silicon-via passing completely through a silicon wafer or die is clearly important in creating 3-D packages."  We clearly agree!

Meetings:

  •  3D IC Integration: The Next Generation of Electronics — Is scheduled for 6:00 PM on Wednesday, March 10, 2010, in Santa Clara.  The event will be hosted by the IEEE Components, Packaging and Manufacturing Technology Society, Santa Clara Valley Chapter.  The topic and speaker both look very interesting.  I'll see you there.

  •  IEEE SCV EDS Symposium: 3D Interconnect - Shaping Future Technology — This outstanding event was held January 29, 2010, in Santa Clara.  The focus was on the progress and challenges in commercializing vertical integration technology.  I blogged about the event  Semiconductor International also wrote a really nice (and much more complete) summary of the event that includes many of the illustrations.

Books:

  •  Handbook of 3D Integration:  Technology and Applications of 3D Integrated Circuits — At nearly 800 pages, this book certainly has the weight to be the definitive work on vertical integration.  Unfortunately, the extremely high price (US$223.02) and rapid pace of innovation (the book was published Oct-2008) force me to question whether it's worth acquiring.  So far, I've resisted, but I'm sure that the background information would be quite useful.